Field of the Disclosure
The present disclosure relates generally to integrated circuit devices and, more particularly, standard-cell based design and fabrication of integrated circuit devices.
Description of the Related Art
Cell-based design methodologies permit application-specific integrated circuits (ASICs), Systems-on-a-chip (SoCs), and other complex integrated circuit (IC) structures to be efficiently designed by abstracting a digital function of the IC structure. In such methodologies, a standard cell is a collection of gate-level elements and interconnection structures standardized at a functional level. There are a number of standard cells providing different functions that typically are pre-designed and pre-verified, and then collected into a library. Electronic design automation (EDA) tools then may use this standard cell library in designing the physical layout of an integrated circuit (IC). One such EDA tool is a place and route tool, which builds the physical layout of an IC design from the cells represented by the standard cell library. The place and route tool places the cells side-by-side and uses a routing tool to electrically connect the cells in a specified way to implement corresponding logic of the IC design.
To ensure that an IC design using standard cells can be manufactured by a semiconductor foundry, the semiconductor foundry typically supplies the designer with a set of design rules that apply to a specified technology process, whereby these design rules specify various parameters pertaining to spacing, width, enclosure, and extension for the physical elements within the physical layout of the IC design. A design rule check (DRC) tool thus applies the specified design rules to the IC design to verify that all design rules are met and thus the IC may be fabricated as designed using the specified technology process.